Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access

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1999 17TH IEEE VLSI Test Symposium

San Diego, California

April 26-April 30

ISBN: 0-7695-0146-X

	ASCII Text	x
	Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles Stroud, "Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access," VLSI Test Symposium, IEEE, pp. 413, 1999 17TH IEEE VLSI Test Symposium, 1999.

	BibTex	x
	@article{ 10.1109/VTEST.1999.766697, author = {Carter Hamilton and Gretchen Gibson and Sajitha Wijesuriya and Charles Stroud}, title = {Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1999}, issn = {1093-0167}, pages = {413}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766697}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access SN - 1093-0167 SP EP A1 - Carter Hamilton, A1 - Gretchen Gibson, A1 - Sajitha Wijesuriya, A1 - Charles Stroud, PY - 1999 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Carter Hamilton, University of Kentucky

Gretchen Gibson, University of Kentucky

Sajitha Wijesuriya, University of Kentucky

Charles Stroud, University of Kentucky

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766697

Four methods for accessing BIST for FPGAs via the IEEE 1149.1 standard Boundary Scan interface are presented and discussed in terms of advantages/disadvantages including their impact on test time and diagnostic resolution. These methods can be used in a variety of FPGA architectures for system level testing and diagnosis

Citation:

Carter Hamilton, Gretchen Gibson, Sajitha Wijesuriya, Charles Stroud, "Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access," vts, pp.413, 1999 17TH IEEE VLSI Test Symposium, 1999

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