1999 17TH IEEE VLSI Test Symposium Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits San Diego, California April 26-April 30 ISBN: 0-7695-0146-X
This paper proposes a new class of codes termed "weight-based codes" where each output bit is assigned a weight and the check bits represent the sum of the weights of the output bits which have value '1'. A Berger code is a special member of this proposed class of codes where each output bit is assigned a weight of one. This paper describes the application of these codes for the efficient on-line error detection of arbitrary multilevel circuits. The overall probability of detecting any number of erroneous bits at the output caused by a single internal fault is shown to be higher for weight-based codes than standard error detecting codes. Further, a very efficient design exists for the checker. The checker is area and speed efficient, has low power consumption, and can be tested by a small set of incoming code words. There is always a tradeoff between the fault detection capability and area overhead requirement of an error detecting code. Weight-based codes present a controlled way of increasing the number of check bits to achieve a desired fault detection capability.
Citation:
Debaleena Das, Nur A. Touba, "Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits," vts, pp.370, 1999 17TH IEEE VLSI Test Symposium, 1999 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||