1999 17TH IEEE VLSI Test Symposium
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits
San Diego, California
April 26-April 30
ISBN: 0-7695-0146-X
We present three new procedures for identifying undetectable and redundant faults in synchronous sequential circuits. The cedures use an iterative logic array of limited length, into which faults are injected in different ways. The proposed procedures help identify undetectable and redundant faults that cannot be identified by existing procedures based on iterative logic arrays of limited length.
Citation:
Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin, "Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits," vts, pp.275, 1999 17TH IEEE VLSI Test Symposium, 1999
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