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1999 17TH IEEE VLSI Test Symposium
REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
San Diego, California
April 26-April 30
ISBN: 0-7695-0146-X
ASCII Text
x 
 
Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer, "REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment," VLSI Test Symposium, IEEE, pp. 268, 1999 17TH IEEE VLSI Test Symposium, 1999.
 
 
BibTex
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@article{ 10.1109/VTEST.1999.766675,
author = {Michael R. Grimaila and Sooryong Lee and Jennifer Dworak and Kenneth M. Butler and Bret Stewart and Hari Balachandran and Bryan Houchins and Vineet Mathur and Jaehong Park and Li-C. Wang and M. Ray Mercer},
title = {REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1999},
issn = {1093-0167},
pages = {268},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766675},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment
SN - 1093-0167
SP
EP
A1 - Michael R. Grimaila,
A1 - Sooryong Lee,
A1 - Jennifer Dworak,
A1 - Kenneth M. Butler,
A1 - Bret Stewart,
A1 - Hari Balachandran,
A1 - Bryan Houchins,
A1 - Vineet Mathur,
A1 - Jaehong Park,
A1 - Li-C. Wang,
A1 - M. Ray Mercer,
PY - 1999
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
For many years, non-target detection experiments have been simulated by using AND/OR bridges or gross delay faults as surrogates. For example, the defective part level can be estimated based upon surrogate detection when test patterns target stuck-at faults in the circuit. For the first time, test pattern generation techniques that attempt to maximize non-target defect detection have been used to test a real, 100% scanned, commercial chip consisting of 75K logic gates. In this experiment, the defective part level for REDO-based patterns was 1,288 parts per million lower than that achieved by DC stuck-at based patterns generated using today's state of the art tools and techniques.
Citation:
Michael R. Grimaila, Sooryong Lee, Jennifer Dworak, Kenneth M. Butler, Bret Stewart, Hari Balachandran, Bryan Houchins, Vineet Mathur, Jaehong Park, Li-C. Wang, M. Ray Mercer, "REDO - Probabilistic Excitation and Deterministic Observation - First Commercial Experiment," vts, pp.268, 1999 17TH IEEE VLSI Test Symposium, 1999
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