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1999 17TH IEEE VLSI Test Symposium
Implication and Evaluation Techniques for Proving Fault Equivalence
San Diego, California
April 26-April 30
ISBN: 0-7695-0146-X
ASCII Text
x 
 
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana, "Implication and Evaluation Techniques for Proving Fault Equivalence," VLSI Test Symposium, IEEE, pp. 201, 1999 17TH IEEE VLSI Test Symposium, 1999.
 
 
BibTex
x
 
@article{ 10.1109/VTEST.1999.766666,
author = {M. Enamul Amyeen and W. Kent Fuchs and Irith Pomeranz and Vamsi Boppana},
title = {Implication and Evaluation Techniques for Proving Fault Equivalence},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1999},
issn = {1093-0167},
pages = {201},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766666},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Implication and Evaluation Techniques for Proving Fault Equivalence
SN - 1093-0167
SP
EP
A1 - M. Enamul Amyeen,
A1 - W. Kent Fuchs,
A1 - Irith Pomeranz,
A1 - Vamsi Boppana,
PY - 1999
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
M. Enamul Amyeen, Purdue University
W. Kent Fuchs, Purdue University
Irith Pomeranz, University of Iowa
Vamsi Boppana, Fujitsu Labs of America
Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence.
Citation:
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana, "Implication and Evaluation Techniques for Proving Fault Equivalence," vts, pp.201, 1999 17TH IEEE VLSI Test Symposium, 1999
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