Delay Fault Testing of Designs with Embedded IP Cores

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	Similar Articles Articles by Hyungwon Kim Articles by John P. Hayes

1999 17TH IEEE VLSI Test Symposium

San Diego, California

April 26-April 30

ISBN: 0-7695-0146-X

	ASCII Text	x
	Hyungwon Kim, John P. Hayes, "Delay Fault Testing of Designs with Embedded IP Cores," VLSI Test Symposium, IEEE, pp. 160, 1999 17TH IEEE VLSI Test Symposium, 1999.

	BibTex	x
	@article{ 10.1109/VTEST.1999.766660, author = {Hyungwon Kim and John P. Hayes}, title = {Delay Fault Testing of Designs with Embedded IP Cores}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1999}, issn = {1093-0167}, pages = {160}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766660}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Delay Fault Testing of Designs with Embedded IP Cores SN - 1093-0167 SP EP A1 - Hyungwon Kim, A1 - John P. Hayes, PY - 1999 VL - 0 JA - VLSI Test Symposium, IEEE ER -

Hyungwon Kim, University of Michigan

John P. Hayes, University of Michigan

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766660

Conventional methods cannot effectively verify path delays of designs employing IP circuits (cores) whose implementation details are hidden. A delay fault ATPG method for such designs is proposed that employs a scan technique called selectively transparent scan (STS). Experimental results are presented which show that the STS method can robustly test paths of a specified delay range in core-based circuits, and substantially reduce test length.

Citation:

Hyungwon Kim, John P. Hayes, "Delay Fault Testing of Designs with Embedded IP Cores," vts, pp.160, 1999 17TH IEEE VLSI Test Symposium, 1999

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