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1999 17TH IEEE VLSI Test Symposium
Test Generation for Ground Bounce in Internal Logic Circuitry
San Diego, California
April 26-April 30
ISBN: 0-7695-0146-X
ASCII Text
x 
 
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer, "Test Generation for Ground Bounce in Internal Logic Circuitry," VLSI Test Symposium, IEEE, pp. 95, 1999 17TH IEEE VLSI Test Symposium, 1999.
 
 
BibTex
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@article{ 10.1109/VTEST.1999.766652,
author = {Yi-Shing Chang and Sandeep K. Gupta and Melvin A. Breuer},
title = {Test Generation for Ground Bounce in Internal Logic Circuitry},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1999},
issn = {1093-0167},
pages = {95},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766652},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Test Generation for Ground Bounce in Internal Logic Circuitry
SN - 1093-0167
SP
EP
A1 - Yi-Shing Chang,
A1 - Sandeep K. Gupta,
A1 - Melvin A. Breuer,
PY - 1999
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
Yi-Shing Chang, University of Southern California
Sandeep K. Gupta, University of Southern California
Melvin A. Breuer, University of Southern California
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.
Citation:
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer, "Test Generation for Ground Bounce in Internal Logic Circuitry," vts, pp.95, 1999 17TH IEEE VLSI Test Symposium, 1999
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