G. Parthasarathy, M.L. Bushnell, "10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion," VLSI Test Symposium, IEEE, pp. 210, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670870,
author = {G. Parthasarathy and M.L. Bushnell},
title = {10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {210},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670870},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 10.1 Towards Simultaneous Delay-Fault Built-In Self-Test and Partial-Scan Insertion
SN - 1093-0167
SP
EP
A1 - G. Parthasarathy,
A1 - M.L. Bushnell,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -