H. Yoon, P. Variyam, A. Chatterjee, N. Nagi, "7.4 Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits," VLSI Test Symposium, IEEE, pp. 145, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670862,
author = {H. Yoon and P. Variyam and A. Chatterjee and N. Nagi},
title = {7.4 Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {145},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670862},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 7.4 Hierarchical Statistical Inference Model for Specification Based Testing of Analog Circuits
SN - 1093-0167
SP
EP
A1 - H. Yoon,
A1 - P. Variyam,
A1 - A. Chatterjee,
A1 - N. Nagi,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -