T. Shinogi, T. Hayashi, "6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults," VLSI Test Symposium, IEEE, pp. 112, 16th IEEE VLSI Test Symposium, 1998.

@article{ 10.1109/VTEST.1998.670857,
author = {T. Shinogi and T. Hayashi},
title = {6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1998},
issn = {1093-0167},
pages = {112},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1998.670857},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}

TY - CONF
JO - VLSI Test Symposium, IEEE
TI - 6.2 A Simple and Efficient Method for Generating Compact IDDQ Test Set for Bridging Faults
SN - 1093-0167
SP
EP
A1 - T. Shinogi,
A1 - T. Hayashi,
PY - 1998
VL - 0
JA - VLSI Test Symposium, IEEE
ER -