Integrating on-chip temperature sensors into DfT schemes and BIST architectures

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15th IEEE VLSI Test Symposium (VTS'97)

Monterey, California

April 27-May 01

ISBN: 0-8186-7810-0

	ASCII Text	x
	V. Szekely, M. Rencz, B. Courtois, "Integrating on-chip temperature sensors into DfT schemes and BIST architectures," VLSI Test Symposium, IEEE, pp. 440, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.600330, author = {V. Szekely and M. Rencz and B. Courtois}, title = {Integrating on-chip temperature sensors into DfT schemes and BIST architectures}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {440}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600330}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Integrating on-chip temperature sensors into DfT schemes and BIST architectures SN - 0-8186-7810-0 SP EP A1 - V. Szekely, A1 - M. Rencz, A1 - B. Courtois, PY - 1997 KW - CMOS integrated circuits; on-chip low-power small-area CMOS temperature sensor; BIST; integrated circuit testing; DfTT; design for thermal testability; safety-critical circuit VL - 0 JA - VLSI Test Symposium, IEEE ER -

V. Szekely, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary

M. Rencz, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary

B. Courtois, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600330

The continuously increasing power densities in integrated circuits necessitated the introduction of DfTT (Design for Thermal Testability) design methodology to prevent overheating effects. Newly developed CMOS temperature sensors enable the application of DfTT principle in safety-critical circuits. Parameters and operation principles of the low-power small-area temperature sensor family are presented in details in the paper, followed by the discussion of placement and testing strategies.

Index Terms:

CMOS integrated circuits; on-chip low-power small-area CMOS temperature sensor; BIST; integrated circuit testing; DfTT; design for thermal testability; safety-critical circuit

Citation:

V. Szekely, M. Rencz, B. Courtois, "Integrating on-chip temperature sensors into DfT schemes and BIST architectures," vts, pp.440, 15th IEEE VLSI Test Symposium (VTS'97), 1997

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