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15th IEEE VLSI Test Symposium (VTS'97)
A linear code-preserving signature analyzer COPMISR
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
A. Hlawiczka, Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
M. Gossel, Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
E.S. Sogormonyan, Inst. of Electronics., Silesian Tech. Univ., Gliwice, Poland
In this paper for an arbitrary linear separable code the concept of a COde Preserving Multi-Input Signature Register COPMISR is introduced. For a code with k control bits 2/sup k2/ different COPMISR's can be designed. The optimum COPMISR with a minimum number of XOR-gates can be chosen from this large set. By different examples it is shown how the newly introduced COPMISR can be simultaneously utilized for concurrent checking, testing and localization of an eventually erroneous component of the monitored system. Since parity codes, group-parity codes, duplication codes and Hamming codes are special linear separable codes the concept of the COPMISR has a wide range of applications in different areas of on-line error detection and BIST.
Index Terms:
linear codes; signature analyzer; linear separable code; code preserving multi-input signature register; COPMISR; XOR-gate; concurrent checking; parity code; group -parity code; duplication code; Hamming code; on-line error detection; BIST
Citation:
A. Hlawiczka, M. Gossel, E.S. Sogormonyan, "A linear code-preserving signature analyzer COPMISR," vts, pp.350, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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