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15th IEEE VLSI Test Symposium (VTS'97)
Static logic implication with application to redundancy identification
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
J.-K. Zhao, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
E.M. Rudnick, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
J.H. Patel, Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
This paper presents a new static logic implication algorithm. An improved implication procedure that fully takes advantage of the special context of static implication, the iterative method, and set algebra is described. The algorithm discovers at low cost many indirect implications which are not discovered by dynamic learning without tremendous time cost. The experimental results show that a very large number of indirect implications are found by our algorithm. The static implication procedure has many useful applications, one of which is static redundancy identification. Use of the static implications obtained from the algorithm in static redundancy identification for ISCAS85 combinational circuits resulted in a larger number of redundant faults identified than in previous methods.
Index Terms:
redundancy; static logic implication; redundancy identification; iterative method; set algebra; indirect implications; redundant faults; static learning algorithm
Citation:
J.-K. Zhao, E.M. Rudnick, J.H. Patel, "Static logic implication with application to redundancy identification," vts, pp.288, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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