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15th IEEE VLSI Test Symposium (VTS'97)
A new approach for testing artificial neural networks
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
C.A. Fleischer, Dept. of Electr. & Comput. Eng., Marquette Univ., Milwaukee, WI, USA
L.A. Belfore, II, Dept. of Electr. & Comput. Eng., Marquette Univ., Milwaukee, WI, USA
This paper presents progress on a new and novel testing approach for detecting interconnection deletion faults in electronic implementations of artificial neural networks (ANNs). The testing approach is based on an unusual transient behavior manifested by faulted ANNs showing better apparent performance than fault-free ANNs, when neurons are operated with low activation function gains. The result presented in this paper improves on prior results by requiring fewer test patterns.
Index Terms:
neural chips; testing; artificial neural networks; interconnection deletion faults; transient behavior; faulted ANN; activation function gains
Citation:
C.A. Fleischer, L.A. Belfore, II, "A new approach for testing artificial neural networks," vts, pp.245, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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