Exact probabilistic analysis of error detection for parity checkers

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15th IEEE VLSI Test Symposium (VTS'97)

Monterey, California

April 27-May 01

ISBN: 0-8186-7810-0

	ASCII Text	x
	V.A. Vardanian, "Exact probabilistic analysis of error detection for parity checkers," VLSI Test Symposium, IEEE, pp. 222, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.600276, author = {V.A. Vardanian}, title = {Exact probabilistic analysis of error detection for parity checkers}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {222}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600276}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Exact probabilistic analysis of error detection for parity checkers SN - 0-8186-7810-0 SP EP A1 - V.A. Vardanian, PY - 1997 KW - combinational circuits; probabilistic analysis; error detection; parity checker; latency; single stuck-at fault; circuit under check; multi-output supergate; combinational CUC; restricted observability; restricted detectability; concurrent checker VL - 0 JA - VLSI Test Symposium, IEEE ER -

V.A. Vardanian, Armenian Nat. Academy of Sci., American Univ. of Armenia, Yerevan, Armenia

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600276

Error detection probability and latency of the parity checker with respect to single stuck-at faults in the circuit under check (CUC) are calculated analytically. A notion of "multi-output supergate" is introduced for multi-output combinational CUC generalizing the formerly known notion of (single-output) supergate. "Restricted" observabilities and detectabilities are calculated for each line in the CUC with respect to non-empty subsets of outputs of the CUC. The method may be easily extended for other concurrent checkers as well.

Index Terms:

combinational circuits; probabilistic analysis; error detection; parity checker; latency; single stuck-at fault; circuit under check; multi-output supergate; combinational CUC; restricted observability; restricted detectability; concurrent checker

Citation:

V.A. Vardanian, "Exact probabilistic analysis of error detection for parity checkers," vts, pp.222, 15th IEEE VLSI Test Symposium (VTS'97), 1997

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