Critical hazard free test generation for asynchronous circuits

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	Similar Articles Articles by A. Khoche Articles by E. Brunvand

15th IEEE VLSI Test Symposium (VTS'97)

Monterey, California

April 27-May 01

ISBN: 0-8186-7810-0

	ASCII Text	x
	A. Khoche, E. Brunvand, "Critical hazard free test generation for asynchronous circuits," VLSI Test Symposium, IEEE, pp. 203, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.600270, author = {A. Khoche and E. Brunvand}, title = {Critical hazard free test generation for asynchronous circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {203}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600270}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Critical hazard free test generation for asynchronous circuits SN - 0-8186-7810-0 SP EP A1 - A. Khoche, A1 - E. Brunvand, PY - 1997 KW - asynchronous circuits; self-timed control circuits; asynchronous circuits; critical hazard-free tests; six-valued algebra; macro-module library; partial scan based DFT environment; unbounded delay model; D-algorithm VL - 0 JA - VLSI Test Symposium, IEEE ER -

A. Khoche, Sunrise Test Syst., Fremont, CA, USA

E. Brunvand, Sunrise Test Syst., Fremont, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600270

We describe a technique to generate critical hazard-free tests for self-timed control circuits built using a macro-module library, in a partial scan based DFT environment. We propose a six-valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic test pattern generator.

Index Terms:

asynchronous circuits; self-timed control circuits; asynchronous circuits; critical hazard-free tests; six-valued algebra; macro-module library; partial scan based DFT environment; unbounded delay model; D-algorithm

Citation:

A. Khoche, E. Brunvand, "Critical hazard free test generation for asynchronous circuits," vts, pp.203, 15th IEEE VLSI Test Symposium (VTS'97), 1997

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