loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
15th IEEE VLSI Test Symposium (VTS'97)
Diagnostic Test Pattern Generation for Sequential Circuits
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
ASCII Text
x 
 
Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs, hartanto@dtc.hp. com, "Diagnostic Test Pattern Generation for Sequential Circuits," VLSI Test Symposium, IEEE, pp. 196, 15th IEEE VLSI Test Symposium (VTS'97), 1997.
 
 
BibTex
x
 
@article{ 10.1109/VTEST.1997.600264,
author = {Ismed Hartanto and Vamsi Boppana and Janak H. Patel and W. Kent Fuchs and hartanto@dtc.hp. com},
title = {Diagnostic Test Pattern Generation for Sequential Circuits},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1997},
isbn = {0-8186-7810-0},
pages = {196},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.600264},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Diagnostic Test Pattern Generation for Sequential Circuits
SN - 0-8186-7810-0
SP
EP
A1 - Ismed Hartanto,
A1 - Vamsi Boppana,
A1 - Janak H. Patel,
A1 - W. Kent Fuchs,
A1 - hartanto@dtc.hp. com,
PY - 1997
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at a primary input in the modified circuit. Techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits are also presented. Speeding up the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.
Citation:
Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs, hartanto@dtc.hp. com, "Diagnostic Test Pattern Generation for Sequential Circuits," vts, pp.196, 15th IEEE VLSI Test Symposium (VTS'97), 1997
Usage of this product signifies your acceptance of the Terms of Use.