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15th IEEE VLSI Test Symposium (VTS'97)
Polynomial Formal Verification of Multipliers
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
Martin Keim, Institute of Computer Science Albert-Ludwigs-University
Michael Martin, Institute of Computer Science Albert-Ludwigs-University
Bernd Becker, Institute of Computer Science Albert-Ludwigs-University
Rolf Drechsler, Institute of Computer Science Albert-Ludwigs-University
Paul Molitor, Institute of Computer Science Albert-Ludwigs-University
Until recently, verifying multipliers with formal methods was not feasible, even for small input word sizes. About two years ago, a new data structure, called Multiplicative Binary Moment Diagram (*BMD), was introduced for representing arithmetic functions over Boolean variables. Based on this data structure, methods were proposed by which verification of multipliers with input word sizes of up to 256 bits became now feasible. Only experimental data has been provided for these verification methods until now. In this paper we give a formal proof that logic verification using *BMDs is polynomially bounded in both space and time, when applied to the class of Wallace-tree like multipliers.
Index Terms:
Verification, Binary Moment Diagram (BMD), Multiplier
Citation:
Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor, "Polynomial Formal Verification of Multipliers," vts, pp.150, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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