loading...
 This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
15th IEEE VLSI Test Symposium (VTS'97)
Incremental logic rectification
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
Shi-Yu Huang, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kuang-Chien Chen, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Kwang-Ting Cheng, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process as a sequence of partial corrections. Each partial correction reduces the size of the input vector set producing error responses. Compared with existing approaches, this approach is more general, and able to handle circuits with multiple errors. We also formulate the necessary and sufficient condition of general single-gate correction to achieve better results for some circuits with a single error. To handle larger circuits, we develop a hybrid approach that makes use of the information of structural correspondence between specification and implementation. Experimental results on industrial examples as well as ISCAS85 benchmark circuits are presented to show the effectiveness of our approach.
Index Terms:
logic CAD; incremental logic rectification; incorrect combinational circuit; symbolic BDD techniques; sequence of partial corrections; circuits with multiple errors; general single-gate correction; hybrid approach; structural correspondence; specification; implementation; ISCAS85 benchmark circuits; VLSI design; error region pruning
Citation:
Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, "Incremental logic rectification," vts, pp.143, 15th IEEE VLSI Test Symposium (VTS'97), 1997
Usage of this product signifies your acceptance of the Terms of Use.