Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology, high operating frequency, and short rise/fall times, ground bounce due to switching in internal circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.