Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are not properly adapted. This paper presents two different methods to minimize the test length without sacrificing fault coverage. The simulation-based reseeding method is suited to random pattern testable circuits and uses forward and reverse order simulation to skip ineffective patterns. The analytical method is appropriate for circuits with "hard" faults that are detected only by few test patterns. This method searches for an optimal input value of the accumulator and calculates the best seed analytically. The results show significant test length reductions. The proposed pattern generators can be implemented very efficiently in hardware using available blocks of a data path or in software using an embedded processor.