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15th IEEE VLSI Test Symposium (VTS'97)
Experimental fault analysis of 1 Mb SRAM chips
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
ASCII Text
x 
 
H. Goto, S. Nakamura, K. Iwasaki, "Experimental fault analysis of 1 Mb SRAM chips," VLSI Test Symposium, IEEE, pp. 31, 15th IEEE VLSI Test Symposium (VTS'97), 1997.
 
 
BibTex
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@article{ 10.1109/VTEST.1997.599438,
author = {H. Goto and S. Nakamura and K. Iwasaki},
title = {Experimental fault analysis of 1 Mb SRAM chips},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1997},
isbn = {0-8186-7810-0},
pages = {31},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.599438},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - Experimental fault analysis of 1 Mb SRAM chips
SN - 0-8186-7810-0
SP
EP
A1 - H. Goto,
A1 - S. Nakamura,
A1 - K. Iwasaki,
PY - 1997
KW - SRAM chips; SRAM chips; fault analysis; stuck-at cell faults; stuck-at bit-line faults; stuck-at word-line fault; neighborhood-pattern-sensitive faults; load capacity; margin fault detection; memory testing; 1 Mbit; 70 C; 30 pF
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
H. Goto, Fac. of Eng., Chiba Univ., Japan
S. Nakamura, Fac. of Eng., Chiba Univ., Japan
K. Iwasaki, Fac. of Eng., Chiba Univ., Japan
Analyzing 1,000 faulty 1 Mb SRAM chips that were randomly selected from a single manufacture, we found 251 stuck-at cell faults, 5 stuck-at bit-line faults, 1 stuck-at word-line fault, 46 neighborhood-pattern-sensitive faults, and other kinds of faults. Under the condition that I/sub dd/=4.5 I; temperature=70/spl deg/C, and load capacity C/sub L/=30 pF, we detected margin faults in 460 chips. Because the actual fault data for SRAM chips is rarely reported, the data in this manuscript are very useful and should be of practical importance.
Index Terms:
SRAM chips; SRAM chips; fault analysis; stuck-at cell faults; stuck-at bit-line faults; stuck-at word-line fault; neighborhood-pattern-sensitive faults; load capacity; margin fault detection; memory testing; 1 Mbit; 70 C; 30 pF
Citation:
H. Goto, S. Nakamura, K. Iwasaki, "Experimental fault analysis of 1 Mb SRAM chips," vts, pp.31, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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