Assessing SRAM test coverage for sub-micron CMOS technologies

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	Similar Articles Articles by V. Kim Articles by T. Chen

15th IEEE VLSI Test Symposium (VTS'97)

Monterey, California

April 27-May 01

ISBN: 0-8186-7810-0

	ASCII Text	x
	V. Kim, T. Chen, "Assessing SRAM test coverage for sub-micron CMOS technologies," VLSI Test Symposium, IEEE, pp. 24, 15th IEEE VLSI Test Symposium (VTS'97), 1997.

	BibTex	x
	@article{ 10.1109/VTEST.1997.599437, author = {V. Kim and T. Chen}, title = {Assessing SRAM test coverage for sub-micron CMOS technologies}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1997}, isbn = {0-8186-7810-0}, pages = {24}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.599437}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Assessing SRAM test coverage for sub-micron CMOS technologies SN - 0-8186-7810-0 SP EP A1 - V. Kim, A1 - T. Chen, PY - 1997 KW - CMOS memory circuits; submicron CMOS technologies; SRAM test coverage assessment; memory fault probability model; physical defects; memory array; stuck-at faults; stuck-open faults; transition faults; coupling faults; data retention faults; memory fault coverages; memory test algorithms; functional fault class coverages; 0.5 to 1 mum VL - 0 JA - VLSI Test Symposium, IEEE ER -

V. Kim, Colorado State University

T. Chen, Colorado State University

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.599437

This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are evaluated based on their functional fault class coverages.

Index Terms:

CMOS memory circuits; submicron CMOS technologies; SRAM test coverage assessment; memory fault probability model; physical defects; memory array; stuck-at faults; stuck-open faults; transition faults; coupling faults; data retention faults; memory fault coverages; memory test algorithms; functional fault class coverages; 0.5 to 1 mum

Citation:

V. Kim, T. Chen, "Assessing SRAM test coverage for sub-micron CMOS technologies," vts, pp.24, 15th IEEE VLSI Test Symposium (VTS'97), 1997

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