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15th IEEE VLSI Test Symposium (VTS'97)
A practical approach to instruction-based test generation for functional modules of VLSI processors
Monterey, California
April 27-May 01
ISBN: 0-8186-7810-0
ASCII Text
x 
 
K. Hatayama, K. Hikone, T. Miyazaki, H. Yamada, "A practical approach to instruction-based test generation for functional modules of VLSI processors," VLSI Test Symposium, IEEE, pp. 17, 15th IEEE VLSI Test Symposium (VTS'97), 1997.
 
 
BibTex
x
 
@article{ 10.1109/VTEST.1997.599436,
author = {K. Hatayama and K. Hikone and T. Miyazaki and H. Yamada},
title = {A practical approach to instruction-based test generation for functional modules of VLSI processors},
journal ={VLSI Test Symposium, IEEE},
volume = {0},
year = {1997},
isbn = {0-8186-7810-0},
pages = {17},
doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1997.599436},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - VLSI Test Symposium, IEEE
TI - A practical approach to instruction-based test generation for functional modules of VLSI processors
SN - 0-8186-7810-0
SP
EP
A1 - K. Hatayama,
A1 - K. Hikone,
A1 - T. Miyazaki,
A1 - H. Yamada,
PY - 1997
KW - VLSI; VLSI processors; functional modules; instruction-based test generation; functional test pattern generation; gate level faults; constrained test generation; ALPS; ALU oriented test pattern generation system
VL - 0
JA - VLSI Test Symposium, IEEE
ER -
 
K. Hatayama, Res. Lab., Hitachi Ltd., Ibaraki, Japan
K. Hikone, Res. Lab., Hitachi Ltd., Ibaraki, Japan
T. Miyazaki, Res. Lab., Hitachi Ltd., Ibaraki, Japan
H. Yamada, Res. Lab., Hitachi Ltd., Ibaraki, Japan
This paper presents a practical approach to functional test pattern generation for gate level faults in functional modules of VLSI processors. Test patterns are generated by constrained test generation and translated to functional test patterns, each of which is a sequence of instructions. In this paper, the outline of instruction-based test generation system, ALPS, is given first, and then constrained test generation is described in detail. Finally, the result of practical application to a VLSI processor is given to illustrate the effectiveness of our approach.
Index Terms:
VLSI; VLSI processors; functional modules; instruction-based test generation; functional test pattern generation; gate level faults; constrained test generation; ALPS; ALU oriented test pattern generation system
Citation:
K. Hatayama, K. Hikone, T. Miyazaki, H. Yamada, "A practical approach to instruction-based test generation for functional modules of VLSI processors," vts, pp.17, 15th IEEE VLSI Test Symposium (VTS'97), 1997
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