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14th IEEE VLSI Test Symposium (VTS '96)
Monitoring power dissipation for fault detection
Princeton, NJ
April 28-May 01
ISBN: 0-8186-7304-4
B. Vinnakota, Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
In this paper, we suggest that the dynamic power dissipation of a circuit can be used to detect faults in it. The change in dissipation caused by a fault can be maximized by applying specific test vectors. For example circuits, we show that the power dissipation can be used to detect faults which do not affect static power dissipation. We also discuss how faults may be detected with a frequency domain analysis. In many cases, the Fourier spectra of the power supply currents in the good and faulty circuits will be very different. Power monitoring is also verified experimentally, for an example circuit.
Index Terms:
CMOS integrated circuits; fault location; monitoring; frequency-domain analysis; integrated circuit testing; VLSI; power dissipation; fault detection; frequency domain analysis; test vectors; power monitoring; CMOS IC testing
Citation:
B. Vinnakota, "Monitoring power dissipation for fault detection," vts, pp.483, 14th IEEE VLSI Test Symposium (VTS '96), 1996
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