14th IEEE VLSI Test Symposium (VTS '96)
ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator
Princeton, NJ
April 28-May 01
ISBN: 0-8186-7304-4
M.B. Amin, Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
B. Vinnakota, Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Sequential circuit fault simulators use the multiple bits in a computer data word to accelerate simulation. We introduce, and implement, a new sequential circuit fault simulator, a parallel pattern parallel fault simulator, ZAMBEZI, which simultaneously simulates multiple faults with multiple vectors in one data word. ZAMBEZI is developed by enhancing the control flow, of existing parallel pattern algorithms. For a very wide range of benchmark circuits, compared to parallel fault and parallel pattern simulators, ZAMBEZI offers either the best, or very close to the best, uniprocessor performance. ZAMBEZI also offers superior performance when parallelized.
Index Terms:
fault diagnosis; logic testing; sequential circuits; circuit analysis computing; integrated logic circuits; parallel algorithms; VLSI; ZAMBEZI; parallel pattern simulator; parallel fault simulation; sequential circuit fault simulator; multiple faults simulation; multiple vectors
Citation:
M.B. Amin, B. Vinnakota, "ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator," vts, pp.438, 14th IEEE VLSI Test Symposium (VTS '96), 1996
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