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14th IEEE VLSI Test Symposium (VTS '96)
Consistently dominant fault model for tristate buffer nets
Princeton, NJ
April 28-May 01
ISBN: 0-8186-7304-4
T.J. Powell, Texas Instrum. Inc., Dallas, TX, USA
Unknown values result from floating and contention type faults on tristate buffer nets thereby causing MISR signature loss during test pattern compression. A Consistently Dominant Fault model is presented that removes the problem and permits fault detection of several problem tristate buffer stuck faults.
Index Terms:
fault diagnosis; logic testing; integrated logic circuits; integrated circuit testing; VLSI; fault location; buffer circuits; ternary logic; multivalued logic circuits; consistently dominant fault model; tristate buffer nets; floating type faults; contention type faults; MISR signature loss; test pattern compression; fault detection; stuck faults
Citation:
T.J. Powell, "Consistently dominant fault model for tristate buffer nets," vts, pp.400, 14th IEEE VLSI Test Symposium (VTS '96), 1996
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