Bridging fault coverage improvement by power supply control

V
VTS
1996
14th IEEE VLSI Test Symposium (VTS '96)
Abstract - Bridging fault coverage improvement by power supply control

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	Similar Articles Articles by M. Renovell Articles by P. Huc Articles by Y. Bertrand

14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	M. Renovell, P. Huc, Y. Bertrand, "Bridging fault coverage improvement by power supply control," VLSI Test Symposium, IEEE, pp. 338, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510877, author = {M. Renovell and P. Huc and Y. Bertrand}, title = {Bridging fault coverage improvement by power supply control}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {338}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510877}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Bridging fault coverage improvement by power supply control SN - 0-8186-7304-4 SP EP A1 - M. Renovell, A1 - P. Huc, A1 - Y. Bertrand, PY - 1996 KW - fault diagnosis; logic testing; VLSI; integrated circuit testing; automatic testing; bridging fault coverage; power supply control; resistance interval; faulty value; parametric model; benchmark circuits; VLSI; logic circuits VL - 0 JA - VLSI Test Symposium, IEEE ER -

M. Renovell, Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

P. Huc, Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

Y. Bertrand, Lab. d'Inf., Robotique et Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, France

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510877

This paper analyses the impact of the power supply voltage on the logical behavior of resistive Bridging Fault. It is theoretically demonstrated that the interval of resistance corresponding to the appearance of a faulty value exponentially increases when the power supply decreases. Using the Parametric Model specifically developed for resistive bridging faults, results of parametric bridging faults simulations on benchmark circuits clearly show an improvement of about 40% when a lower-than-normal power supply is used. Moreover this bridging fault coverage improvement technique doesn't need any additional effort such as Design for Testability or specific Test Pattern Generation.

Index Terms:

fault diagnosis; logic testing; VLSI; integrated circuit testing; automatic testing; bridging fault coverage; power supply control; resistance interval; faulty value; parametric model; benchmark circuits; VLSI; logic circuits

Citation:

M. Renovell, P. Huc, Y. Bertrand, "Bridging fault coverage improvement by power supply control," vts, pp.338, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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