Published research on delay fault testing has largely focused on generating a minimal set of test vector pairs to detect as many delay faults in a circuit as possible. Little regard has been paid to the diagnosability of delay faults in the quest for generating tests which can simultaneously detect a delay fault on many paths, one loses the ability to determine which paths caused a chip failure. In an earlier work [1996] we presented a framework to detect which paths are likely to have caused a chip failure for a set of delay fault tests, and to find the associated likely fabrication process parameter variations. Here, we quantify the diagnosability of a path delay fault for a test, and develop a methodology based on the diagnosis framework presented earlier to determine the diagnosability of each path delay fault detected by a given test set. Furthermore, we apply this approach to find the diagnosability of robust path delay faults for the ISCAS'89 benchmark circuits.