14th IEEE VLSI Test Symposium (VTS '96)
Increasing testability by clock transformation (getting rid of those darn states)
Princeton, NJ
April 28-May 01
ISBN: 0-8186-7304-4
D.E. Long, Sun Microsyst., Menlo Park, CA, USA
We provide a new answer to the fundamental question "Why is sequential test generation so difficult?" the presence of darn (Difficult And Really Needed) states. A darn state is both difficult to reach and required to detect some faults. We introduce a method for identifying darn stares, along with a technique to measure their detrimental effect on the fault coverage. Darn states are the result of detrimental correlation between flip-flops (FFs) sharing the same clock. We propose a novel DFT technique in which FFs are partitioned into different groups having independent clocks during resting. The goal of partitioning is to increase the fault coverage by transforming darn states into easy-to-reach states. The proposed DFT has small area overhead and no performance penalty.
Index Terms:
logic testing; sequential circuits; clocks; flip-flops; design for testability; logic partitioning; testability; clock transformation; sequential test generation; darn states; fault coverage; flip-flops; DFT; partitioning; easy-to-reach states
Citation:
K.B. Rajan, D.E. Long, M. Abramovici, "Increasing testability by clock transformation (getting rid of those darn states)," vts, pp.224, 14th IEEE VLSI Test Symposium (VTS '96), 1996