An asynchronous totally self-checking two-rail code error indicator

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	Similar Articles Articles by N. Gaitanis Articles by D. Gizopoulos Articles by A. Paschalis Articles by P. Kostarakis

14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	N. Gaitanis, D. Gizopoulos, A. Paschalis, P. Kostarakis, "An asynchronous totally self-checking two-rail code error indicator," VLSI Test Symposium, IEEE, pp. 151, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510850, author = {N. Gaitanis and D. Gizopoulos and A. Paschalis and P. Kostarakis}, title = {An asynchronous totally self-checking two-rail code error indicator}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {151}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510850}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - An asynchronous totally self-checking two-rail code error indicator SN - 0-8186-7304-4 SP EP A1 - N. Gaitanis, A1 - D. Gizopoulos, A1 - A. Paschalis, A1 - P. Kostarakis, PY - 1996 KW - error detection; logic testing; delays; VLSI; automatic testing; integrated circuit testing; asynchronous circuits; CMOS logic circuits; asynchronous TSC error indicator; totally self-checking error indicator; concurrent detection; delay faults; two-rail code error indicator; CMOS implementation VL - 0 JA - VLSI Test Symposium, IEEE ER -

N. Gaitanis, Inst. of Inf., NCSR "Demokritos", Athens, Greece

D. Gizopoulos, Inst. of Inf., NCSR "Demokritos", Athens, Greece

A. Paschalis, Inst. of Inf., NCSR "Demokritos", Athens, Greece

P. Kostarakis, Inst. of Inf., NCSR "Demokritos", Athens, Greece

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510850

In this paper an asynchronous TSC two-rail code error indicator is presented. Such an error indicator memorises error indications {00,11} generated by TSC checkers with time duration greater than a tolerant limit T and can be used to detect not only faults that cause logical errors bat also faults that cause additional delays. Thus, concurrent detection, of delay faults inside the checkers is an additional application of the proposed circuit. The proposed TSC error indicator is more efficient than the TSC error indicator presented by Gaitanis (see IEEE Trans. Comput., vol. 34, no. 8, p. 753-61, 1985) which, to the authors' knowledge, is the only existing TSC error indicator in the open literature.

Index Terms:

error detection; logic testing; delays; VLSI; automatic testing; integrated circuit testing; asynchronous circuits; CMOS logic circuits; asynchronous TSC error indicator; totally self-checking error indicator; concurrent detection; delay faults; two-rail code error indicator; CMOS implementation

Citation:

N. Gaitanis, D. Gizopoulos, A. Paschalis, P. Kostarakis, "An asynchronous totally self-checking two-rail code error indicator," vts, pp.151, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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