Development of test programs in a virtual test environment

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14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	M. Miegler, W. Wolz, "Development of test programs in a virtual test environment," VLSI Test Symposium, IEEE, pp. 99, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510842, author = {M. Miegler and W. Wolz}, title = {Development of test programs in a virtual test environment}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {99}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510842}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Development of test programs in a virtual test environment SN - 0-8186-7304-4 SP EP A1 - M. Miegler, A1 - W. Wolz, PY - 1996 KW - integrated circuit testing; integrated circuit design; design for testability; circuit CAD; automatic test software; VLSI; test programs development; virtual test environment; quality-assured mixed-signal test programs; standard test description language; VTML; Virtual Test Modelling Language; standardized description models; test system resources; equivalent simulation models VL - 0 JA - VLSI Test Symposium, IEEE ER -

M. Miegler, Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany

W. Wolz, Inst. of Comput.-Aided Circuit Design, Erlangen-Nurnberg Univ., Germany

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510842

An environment for the efficient development of quality-assured mixed-signal test programs is introduced. The new approach provides links between design and test engineers based on a standard test description language VTML (Virtual Test Modelling Language). The language provides standardized description models for test system resources which can be mapped as well to equivalent simulation models as to real world test system hardware. Methods are provided to check the data consistency of test programs and to validate test program behavior using simulation models.

Index Terms:

integrated circuit testing; integrated circuit design; design for testability; circuit CAD; automatic test software; VLSI; test programs development; virtual test environment; quality-assured mixed-signal test programs; standard test description language; VTML; Virtual Test Modelling Language; standardized description models; test system resources; equivalent simulation models

Citation:

M. Miegler, W. Wolz, "Development of test programs in a virtual test environment," vts, pp.99, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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