This paper presents H-SCAN, a practical testing methodology that can be easily applied to a high-level design specification. H-SCAN allows the use of combinational test patterns without the high area and test application time overheads associated with full-scan testing. Connectivities between registers existing in an RT-level design are exploited to reduce the area overhead associated with implementing a scan scheme. Test application time is significantly reduced by using the parallelism inherent in the design, and eliminating the pin constraint of parallel scan schemes by analyzing the test responses on-chip using existing comparators. The proposed method also includes generating appropriate sequential test vectors from combinational test vectors generated by a combinational ATPG program. Application of H-SCAN to RT-level designs and fault simulation using the test patterns generated by H-SCAN shows fault coverage comparable to full-scan testing, with significant reduction in test area overhead and test application time when compared to a traditional gate-level full-scan implementation.