14th IEEE VLSI Test Symposium (VTS '96) A new digital test approach for analog-to-digital converter testing Princeton, NJ April 28-May 01 ISBN: 0-8186-7304-4
A fully digital built-in self-test (BIST) for analog-to-digital converters is presented in this paper. This test circuit is capable of measuring the DNL, INL, offset error and gain error, and mainly consists of several registers and some digital subtracters. The main advantage of this BIST is the ability to test DNL and INL for all codes in the digital domain, which in turn eliminate the necessity of calibration. On the other hand, some parts of the analog-to-digital converter with minor modifications are used in the BIST simultaneously. This also reduces the area overhead and the cost of the test. The proposed BIST structure presents a compromise between test accuracy, area overhead and test cost. The BIST circuitry has been designed using CMOS 1.5 /spl mu/m technology. The simulation results of the test show that it can be applied to medium resolution analog-to-digital converter or high resolution pipelined analog-to-digital converter. The presented BIST shows satisfactory results for 9-bit pipelined analog-to-digital converter.
Index Terms:
analogue-digital conversion; integrated circuit testing; built-in self test; CMOS integrated circuits; VLSI; digital test approach; analog/digital converter testing; built-in self-test; BIST circuitry; offset error; gain error; DNL; INL; area overhead reduction; CMOS technology; medium resolution ADC; high resolution pipelined ADC; A/D converter testing; differential nonlinearity; integral nonlinearity; 1.5 micron
Citation:
M. Ehsanian, B. Kaminska, K. Arabi, "A new digital test approach for analog-to-digital converter testing," vts, pp.60, 14th IEEE VLSI Test Symposium (VTS '96), 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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