Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design

V
VTS
1996
14th IEEE VLSI Test Symposium (VTS '96)
Abstract - Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design

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14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	D. Vazquez, J.L. Huertas, A. Rueda, "Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design," VLSI Test Symposium, IEEE, pp. 42, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510833, author = {D. Vazquez and J.L. Huertas and A. Rueda}, title = {Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {42}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510833}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design SN - 0-8186-7304-4 SP EP A1 - D. Vazquez, A1 - J.L. Huertas, A1 - A. Rueda, PY - 1996 KW - design for testability; integrated circuit testing; analogue integrated circuits; operational amplifiers; CMOS analogue integrated circuits; integrated circuit design; DFT; analog integrated circuits; sw-op amp design; IC testing; CMOS implementations; power dissipation; area; design efforts; cell design VL - 0 JA - VLSI Test Symposium, IEEE ER -

D. Vazquez, Centro Nacional de Microelectron., Seville Univ., Spain

J.L. Huertas, Centro Nacional de Microelectron., Seville Univ., Spain

A. Rueda, Centro Nacional de Microelectron., Seville Univ., Spain

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510833

This paper focuses on the implementation of the 'sw-op amp' concept for analog circuits testing. Some alternative CMOS implementations are presented and compared in terms of influential parameters from a performance and cost point of view. Results show that the impact on the performance, power dissipation, and cost in terms of area and design efforts provoked by the use of sw-opamp structures, can be significantly reduced through efficient design of this cell.

Index Terms:

design for testability; integrated circuit testing; analogue integrated circuits; operational amplifiers; CMOS analogue integrated circuits; integrated circuit design; DFT; analog integrated circuits; sw-op amp design; IC testing; CMOS implementations; power dissipation; area; design efforts; cell design

Citation:

D. Vazquez, J.L. Huertas, A. Rueda, "Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design," vts, pp.42, 14th IEEE VLSI Test Symposium (VTS '96), 1996

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