Scan insertion criteria for low design impact

V
VTS
1996
14th IEEE VLSI Test Symposium (VTS '96)
Abstract - Scan insertion criteria for low design impact

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by S. Barbagallo Articles by M. Lobetti Bodoni Articles by D. Medina Articles by F. Corno Articles by P. Prinetto Articles by M. Sonza Reorda

14th IEEE VLSI Test Symposium (VTS '96)

Princeton, NJ

April 28-May 01

ISBN: 0-8186-7304-4

	ASCII Text	x
	S. Barbagallo, M. Lobetti Bodoni, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda, "Scan insertion criteria for low design impact," VLSI Test Symposium, IEEE, pp. 26, 14th IEEE VLSI Test Symposium (VTS '96), 1996.

	BibTex	x
	@article{ 10.1109/VTEST.1996.510831, author = {S. Barbagallo and M. Lobetti Bodoni and D. Medina and F. Corno and P. Prinetto and M. Sonza Reorda}, title = {Scan insertion criteria for low design impact}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1996}, isbn = {0-8186-7304-4}, pages = {26}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510831}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Scan insertion criteria for low design impact SN - 0-8186-7304-4 SP EP A1 - S. Barbagallo, A1 - M. Lobetti Bodoni, A1 - D. Medina, A1 - F. Corno, A1 - P. Prinetto, A1 - M. Sonza Reorda, PY - 1996 KW - boundary scan testing; automatic testing; integrated circuit testing; logic testing; sequential circuits; flip-flops; capacitance; integrated circuit design; application specific integrated circuits; logic CAD; scan insertion criteria; design impact; partial scan; full scan; flip-flop ordering; scan chain; capacitance constraints; layout information; design flow; power dissipation; Italtel Design Environment VL - 0 JA - VLSI Test Symposium, IEEE ER -

S. Barbagallo, Central R&D Dept., Italy

M. Lobetti Bodoni, Central R&D Dept., Italy

D. Medina, Central R&D Dept., Italy

F. Corno, Central R&D Dept., Italy

P. Prinetto, Central R&D Dept., Italy

M. Sonza Reorda, Central R&D Dept., Italy

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1996.510831

The paper focuses an the constraints that the new silicon technologies impose on the implementation of partial and full scan approach. In particular the ordering of Flip-Flops inside each scan chain must be decided taking into account the capacitance constraints imposed by new technologies. The main goal of this paper is to prove that recent technologies impose a new design flow, exploiting layout information for scan chain reordering. Two algorithms are then described, which reduce both the average and the maximum distance between FFs in the chains, thus reducing the power dissipation of the circuit, too. Preliminary results, obtained through the implementation of the algorithms in the Italtel Design Environment and their application on a sample circuit, are reported.

Index Terms:

boundary scan testing; automatic testing; integrated circuit testing; logic testing; sequential circuits; flip-flops; capacitance; integrated circuit design; application specific integrated circuits; logic CAD; scan insertion criteria; design impact; partial scan; full scan; flip-flop ordering; scan chain; capacitance constraints; layout information; design flow; power dissipation; Italtel Design Environment

Citation:

S. Barbagallo, M. Lobetti Bodoni, D. Medina, F. Corno, P. Prinetto, M. Sonza Reorda, "Scan insertion criteria for low design impact," vts, pp.26, 14th IEEE VLSI Test Symposium (VTS '96), 1996

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.