14th IEEE VLSI Test Symposium (VTS '96) Design of a fast, easily testable ALU Princeton, NJ April 28-May 01 ISBN: 0-8186-7304-4
The design and implementation of a fast, easily testable arithmetic-logic unit (ALU) is described. It is built around an adder design which is level-testable (L-testable), implying that the number of test patterns required to detect all functional faults in modules grows logarithmically with the size of the ALU. L-testability is achieved by exploiting some inherent properties of carry-lookahead addition. The resulting ALU design requires only two extra inputs, regardless of the size of the ALU. For an 8-bit implementation that has little impact on performance, the area overhead is shown to be less than 9%.
Index Terms:
adders; digital arithmetic; logic arrays; fault diagnosis; logic testing; integrated circuit testing; automatic testing; carry logic; integrated circuit design; ALU; arithmetic-logic unit; adder design; L-testable design; level-testable; test patterns; functional faults; carry-lookahead addition; area overhead; 8 bit
Citation:
R.D. Blanton, J.P. Hayes, "Design of a fast, easily testable ALU," vts, pp.9, 14th IEEE VLSI Test Symposium (VTS '96), 1996 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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