A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers

V
VTS
1995
13th IEEE VLSI Test Symposium (VTS'95)
Abstract - A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers

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	Similar Articles Articles by S. Brown Articles by G. Gutierrez Articles by R. Nelson Articles by C. VanKrevelen

13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	S. Brown, G. Gutierrez, R. Nelson, C. VanKrevelen, "A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers," VLSI Test Symposium, IEEE, pp. 0467, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512676, author = {S. Brown and G. Gutierrez and R. Nelson and C. VanKrevelen}, title = {A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0467}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512676}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers SN - 0-8186-7000-2 SP EP A1 - S. Brown, A1 - G. Gutierrez, A1 - R. Nelson, A1 - C. VanKrevelen, PY - 1995 KW - emitter-coupled logic; logic arrays; clocks; timing; automatic test equipment; programmable controllers; triple channel ATE controller; gate array; timing verniers; high speed testing; precision edge timing; drive waveforms; returning signals; system clock frequency; ECL; 500 MHz; 40 ps VL - 0 JA - VLSI Test Symposium, IEEE ER -

S. Brown, AMCC, San Diego, CA, USA

G. Gutierrez, AMCC, San Diego, CA, USA

R. Nelson, AMCC, San Diego, CA, USA

C. VanKrevelen, AMCC, San Diego, CA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512676

Abstract: An integrated circuit for high speed testing which provides precision edge timing and control for three complete channels is described. It consists of nine timing verniers of 40 pS time-step, 80 pS accuracy and 2 nS full range, and all the logic required to configure the drive waveforms and the strobe of the returning signals. The system clock frequency into the IC is 500 MHz.

Index Terms:

emitter-coupled logic; logic arrays; clocks; timing; automatic test equipment; programmable controllers; triple channel ATE controller; gate array; timing verniers; high speed testing; precision edge timing; drive waveforms; returning signals; system clock frequency; ECL; 500 MHz; 40 ps

Citation:

S. Brown, G. Gutierrez, R. Nelson, C. VanKrevelen, "A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers," vts, pp.0467, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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