13th IEEE VLSI Test Symposium (VTS'95)
Synthesis of combinational circuits with special fault-handling capabilities
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
Abstract: In this paper we present a new approach to the design of circuits with special properties with regards to internal faults, such as self-checking and fault-tolerant circuits. The approach is based on introducing a minimal amount of redundancy during a multilevel logic optimization process. In this process, we take advantage of the degrees of freedom associated with internal don't care conditions, in order to minimize the amount of redundancy needed to achieve the desired fault-handling capabilities. Experimental results on several benchmark circuits are presented. They compare very favourably with traditional implementations based on topological augmentation rules.
Index Terms:
redundancy; multivalued logic; design for testability; logic CAD; circuit optimisation; logic design; circuit reliability; combinational circuits; logic testing; combinational circuit synthesis; fault-handling capabilities; internal faults; self-checking circuits; fault-tolerant circuits; redundancy; multilevel logic optimization process
Citation:
A. Bogliolo, M. Damiani, "Synthesis of combinational circuits with special fault-handling capabilities," vts, pp.0454, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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