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13th IEEE VLSI Test Symposium (VTS'95)
Synthesis of locally exhaustive test pattern generators
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
G. Kemnitz, Inst. fur Tech. Inf., Tech. Univ. Dresden, Germany
Abstract: Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compute the linear sums for real circuits up to several hundreds of inputs and outputs. The idea is to substitute a strategy of introducing fresh variables into an array of sums for the former linear independence test. This reduces the complexity of the calculation on an enormous scale. Experiments with several hundred randomly selected cone structures allow the rough estimation that the so computed generators are on average smaller than shift register based ones if the number of equal size cones is not larger than the number of inputs of the circuit under test.
Index Terms:
integrated circuit testing; logic testing; automatic testing; locally exhaustive TPG; test pattern generators; linear sum computation; TPG synthesis
Citation:
G. Kemnitz, "Synthesis of locally exhaustive test pattern generators," vts, pp.0440, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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