Abstract: A new design methodology for a pattern generator is proposed, formulated in the context of on-chip BIST. The pattern generator consists of two components: a GLFSR, earlier proposed as a pseudo-random pattern generator, and combinational logic, to snap the outputs of the pseudo-random pattern generator. Using fewer test patterns with only a small area overhead, this combinatorial logic block, for a particular CUT, can be designed to achieve nearly 100% single stuck-at fault coverage. Specifically, where weighted pattern generators only enhance the probability of testing a specified set of hard-to-detect faults, the proposed combinational logic, using a comparable hardware overhead, can guarantee generating the test for those faults. Experimental results demonstrate that under identical conditions, the fault coverage of the proposed pattern generator is significantly higher, compared to the conventional weighted pattern generation techniques. For enhancing effectiveness, this combinational logic mapping technique can also be used to augment any weighted pattern technique. Because LFSRs are special cases of GLFSRs, our design is more general than LFSR-based designs.