Multifault testability of delay-testable circuits

	This Article
	Subscribers, please Login Purchase article: $19 PDF IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by W. Ke Articles by P.R. Menon

13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	W. Ke, P.R. Menon, "Multifault testability of delay-testable circuits," VLSI Test Symposium, IEEE, pp. 0400, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512667, author = {W. Ke and P.R. Menon}, title = {Multifault testability of delay-testable circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0400}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512667}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Multifault testability of delay-testable circuits SN - 0-8186-7000-2 SP EP A1 - W. Ke, A1 - P.R. Menon, PY - 1995 KW - combinational circuits; logic testing; delays; multivalued logic circuits; delay-testable circuits; multifault testability; path-delay-fault testability; multiple stuck-at-fault testability; multilevel combinational circuits; robust path-delay-fault test set VL - 0 JA - VLSI Test Symposium, IEEE ER -

W. Ke, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

P.R. Menon, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512667

Abstract: This paper investigates the relationship between path-delay-fault testability and multiple stuck-at-fault testability in multilevel combinational circuits. It is shown that a complete robust path-delay-fault test set may not detect all multiple stuck-at faults in multilevel circuits. We also show that path-delay-fault testability does not imply multiple stuck-at-fault testability in multilevel circuits, contradicting a recent paper. Certain path delay tests are also shown to be invalidated by the presence of untestable or untested multiple stuck-at faults.

Index Terms:

combinational circuits; logic testing; delays; multivalued logic circuits; delay-testable circuits; multifault testability; path-delay-fault testability; multiple stuck-at-fault testability; multilevel combinational circuits; robust path-delay-fault test set

Citation:

W. Ke, P.R. Menon, "Multifault testability of delay-testable circuits," vts, pp.0400, 13th IEEE VLSI Test Symposium (VTS'95), 1995

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.