Abstract: Industrial circuits contain, in addition to the binary logic elements [n] and, [n] or and [n] xor gates, other logic elements such as three-state elements, busses and bidirectionals. Previous published work on automatic test pattern generation (ATPG) can not handle all of the above mentioned circuit elements, generates too large test sets, or generates test patterns which can cause circuit damage. A new fast ATPG system for industrial circuits is introduced capable of coping with all of the above mentioned circuit elements, will not cause circuit damage and generates compact test sets using new heuristics for compaction oriented decision making. Experimental results show that the compact test sets are much smaller than in [vdL94b] (on average 60%). The extra ATPG time required for generating these compact test sets is a relatively small penalty compared to the decrease in test set size.