13th IEEE VLSI Test Symposium (VTS'95) CURRENT: a test generation system for I/sub DDQ/ testing Princeton, New Jersey April 30-May 03 ISBN: 0-8186-7000-2
Abstract: This paper presents an I/sub DDQ/ test generation system for scan-based circuits, called CURRENT. A library-based fault modeling strategy is used to specify a realistic target fault set, which encompasses intra-gate shorts (for example stuck-on faults, gate-drain shorts) as well as inter-gate shorts (bridging faults). CURRENT consists of a fault simulator and a deterministic test generator. The fault simulator can be used to determine the fault coverage of a given test set or to generate test patterns for easy-to-detect leakage faults. The deterministic test generator is able to generate tests for hard-to-detect leakage faults and to identify redundant leakage faults. Furthermore, CURRENT is able to generate small test sets through the use of a new test set compaction technique, thus reducing the total test application time for I/sub DDQ/ testing. Experimental results show that CURRENT is able to generate small test sets with a test efficiency of 100% for each of the benchmark circuits with up to 2,400,000 considered leakage faults.
Index Terms:
integrated circuit testing; automatic testing; boundary scan testing; fault diagnosis; logic testing; CMOS logic circuits; fault location; CURRENT test system; test generation system; I/sub DDQ/ testing; scan-based circuits; library-based fault modeling strategy; intra-gate shorts; inter-gate shorts; stuck-on faults; gate-drain shorts; bridging faults; fault simulator; deterministic test generator; fault coverage; leakage faults; test set compaction technique; test application time reduction
Citation:
U. Mahlstedt, J. Alt, M. Heinitz, "CURRENT: a test generation system for I/sub DDQ/ testing," vts, pp.0317, 13th IEEE VLSI Test Symposium (VTS'95), 1995 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||