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13th IEEE VLSI Test Symposium (VTS'95)
Compact test generation for bridging faults under I/sub DDQ/ testing
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
R.S. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S. Kajihara, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract: We propose a procedure to generate compact test sets for bridging faults under I/sub DDQ/ testing. Several techniques are employed to achieve compact test sets. Heuristics developed for stuck-at faults are shown to be effective in this context. The techniques especially designed for bridging faults are based on the observation that the yet-undetected faults can be represented using sets of lines and that a minimum test set size is obtained if the line sets representing yet-undetected faults are halved with every additional test vector. Logic blocks called bit-adders allow the partitioning of the line sets using a test generator for stuck-at faults, without having to determine in advance how the lines in a given set will be divided. Thus partitioning can be performed in a cost effective way for any line set size. Experimental results show that the test sets generated by the proposed procedure are smaller than those obtained by previously proposed procedures.
Index Terms:
CMOS logic circuits; integrated circuit testing; logic testing; fault location; logic partitioning; compact test generation; bridging faults; I/sub DDQ/ testing; stuck-at faults; bit-adders; partitioning
Citation:
R.S. Reddy, I. Pomeranz, S.M. Reddy, S. Kajihara, "Compact test generation for bridging faults under I/sub DDQ/ testing," vts, pp.0310, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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