13th IEEE VLSI Test Symposium (VTS'95)
Diagnosis of interconnects and FPICs using a structured walking-1 approach
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
T. Liu, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
F. Lombardi, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
J. Salinas, Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Abstract: This paper presents a generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs). The proposed structural test method explicitly avoids aliasing and confounding and as applicable to dense as well as sparse layouts. The proposed method is applicable to both one-step and two-step test generation and diagnosis. Two algorithms with an execution complexity of O(n/sup 2/), where n is the number of nets in the interconnect, are given. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. The applicability of the proposed approach to FPICs is discussed and evaluated by simulation.
Index Terms:
integrated circuit testing; boundary scan testing; fault diagnosis; integrated circuit interconnections; automatic testing; field programmable interconnect chips; structured walking-1 approach; interconnects testing; boundary scan architectures; one-step test generation; two-step test generation; diagnosis
Citation:
T. Liu, F. Lombardi, J. Salinas, "Diagnosis of interconnects and FPICs using a structured walking-1 approach," vts, pp.0256, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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