Abstract: Scan based diagnostic schemes are used to diagnose faults in faulty circuits. Such techniques assume that the scan path itself is fault-free. However, the logic circuitry associated with the scan chain may occupy nearly 30% of a chip area and hence warrants consideration during fault diagnosis. In this work we propose a simple extension to the scan chain to diagnose faults in scan chains.
Index Terms:
fault diagnosis; logic testing; integrated circuit testing; integrated logic circuits; design for testability; combinational circuits; scan path failures; scan based diagnostic schemes; faulty circuits; logic circuitry; scan chain fault diagnosis
Citation:
S. Edirisooriya, G. Edirisooriya, "Diagnosis of scan path failures," vts, pp.0250, 13th IEEE VLSI Test Symposium (VTS'95), 1995