13th IEEE VLSI Test Symposium (VTS'95)
VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits
Princeton, New Jersey
April 30-May 03
ISBN: 0-8186-7000-2
Abstract: VISION is an efficient parallel pattern fault simulator for synchronous sequential circuits. VISION is based on an earlier fault simulator called PARIS which was the first and a highly efficient parallel pattern fault simulator. In this paper, we propose four new heuristics which substantially speed up the parallel pattern fault simulation for synchronous sequential circuits. According to our experiments, our fault simulator, VISION, which incorporates the four heuristics, is about 1.6 times faster than PARIS for 16 benchmark circuits.
Index Terms:
fault diagnosis; logic testing; sequential circuits; VLSI; integrated circuit testing; circuit analysis computing; digital simulation; flip-flops; parallel pattern fault simulator; synchronous sequential circuits; VISION; heuristics; benchmark circuits; VLSI
Citation:
R. Nair, Dong Sam Ha, "VISION: an efficient parallel pattern fault simulator for synchronous sequential circuits," vts, pp.0221, 13th IEEE VLSI Test Symposium (VTS'95), 1995
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