Switch-level modeling of transistor-level stuck-at faults

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	Similar Articles Articles by P. Liden Articles by P. Dahlgren

13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	P. Liden, P. Dahlgren, "Switch-level modeling of transistor-level stuck-at faults," VLSI Test Symposium, IEEE, pp. 0208, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512639, author = {P. Liden and P. Dahlgren}, title = {Switch-level modeling of transistor-level stuck-at faults}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0208}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512639}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Switch-level modeling of transistor-level stuck-at faults SN - 0-8186-7000-2 SP EP A1 - P. Liden, A1 - P. Dahlgren, PY - 1995 KW - CMOS logic circuits; fault diagnosis; logic testing; integrated circuit modelling; integrated circuit testing; circuit analysis computing; switch-level modeling; transistor-level stuck-at faults; switch-level algorithms; fault modeling capability; fault detection measures; confidence degradation; unknown output values; uncertainty quantification; node model; CMOS circuits VL - 0 JA - VLSI Test Symposium, IEEE ER -

P. Liden, Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden

P. Dahlgren, Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512639

Abstract: Two new switch-level algorithms with efficient management of unknown values are evaluated with respect to their fault modeling capability. The degradation of confidence in fault detection measures owing to unknown (X) output values is discussed and a strategy to quantify this uncertainty is proposed. It is demonstrated that this uncertainty can be decreased significantly when the node model is extended to include two resistances.

Index Terms:

CMOS logic circuits; fault diagnosis; logic testing; integrated circuit modelling; integrated circuit testing; circuit analysis computing; switch-level modeling; transistor-level stuck-at faults; switch-level algorithms; fault modeling capability; fault detection measures; confidence degradation; unknown output values; uncertainty quantification; node model; CMOS circuits

Citation:

P. Liden, P. Dahlgren, "Switch-level modeling of transistor-level stuck-at faults," vts, pp.0208, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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