Testability of floating gate defects in sequential circuits

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13th IEEE VLSI Test Symposium (VTS'95)

Princeton, New Jersey

April 30-May 03

ISBN: 0-8186-7000-2

	ASCII Text	x
	V.H. Champac, J. Figueras, "Testability of floating gate defects in sequential circuits," VLSI Test Symposium, IEEE, pp. 0202, 13th IEEE VLSI Test Symposium (VTS'95), 1995.

	BibTex	x
	@article{ 10.1109/VTEST.1995.512638, author = {V.H. Champac and J. Figueras}, title = {Testability of floating gate defects in sequential circuits}, journal ={VLSI Test Symposium, IEEE}, volume = {0}, year = {1995}, isbn = {0-8186-7000-2}, pages = {0202}, doi = {http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512638}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - CONF JO - VLSI Test Symposium, IEEE TI - Testability of floating gate defects in sequential circuits SN - 0-8186-7000-2 SP EP A1 - V.H. Champac, A1 - J. Figueras, PY - 1995 KW - fault diagnosis; logic testing; sequential circuits; CMOS logic circuits; flip-flops; integrated circuit modelling; integrated circuit testing; floating gate defect testability; sequential circuits; logic detectability conditions; I/sub DDQ/ testing; defective transistors; logically untestable branches; simulated results; scan path cell; CMOS latch cell; scan path flip-flops VL - 0 JA - VLSI Test Symposium, IEEE ER -

V.H. Champac, Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico

J. Figueras, Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/VTEST.1995.512638

Abstract: The logic detectability conditions of floating gate (FG) defects in sequential circuits are considered. It has been found that a FG defective sequential circuit may be able to memorize one or two logic states depending on the values of the defect parameters. I/sub DDQ/ testing may detect a large class of floating gate defects including some defective transistors located in logically untestable branches. Good agreement is observed between the theoretical and simulated results with experimental measurements performed on a typical scan path cell designed intentionally with floating gate defects.

Index Terms:

fault diagnosis; logic testing; sequential circuits; CMOS logic circuits; flip-flops; integrated circuit modelling; integrated circuit testing; floating gate defect testability; sequential circuits; logic detectability conditions; I/sub DDQ/ testing; defective transistors; logically untestable branches; simulated results; scan path cell; CMOS latch cell; scan path flip-flops

Citation:

V.H. Champac, J. Figueras, "Testability of floating gate defects in sequential circuits," vts, pp.0202, 13th IEEE VLSI Test Symposium (VTS'95), 1995

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